1. Field of the Invention
The present invention relates to a system for treatment of a single-bit error in a buffer storage unit of a set-associative type provided in a data processing device having an error check and correct (ECC) circuit for single-bit error correction and plural-bit error detection.
2. Description of the Prior Art
Storage devices occasionally suffer from errors of data stored in their memory elements. These include bit-inversion errors produced by .alpha.-rays and so on, such errors being known as "soft errors" to distinguish them from "hard errors" caused by hardware malfunctions. Soft errors can be corrected by rewriting the correct data into the memory elements. In prior art storage devices, correction of soft errors has been effected by the method of rewriting the data containing errors using a patrol function or the method of rewriting the data containing errors when that part of the stored data is rewritten in the storage device.
In the first method, it is necessary to access all the memory elements in the storage device. Thus, it takes a long time to correct the data containing errors. In the second method, on the other hand, the error data can be corrected only during partial writing and cannot be corrected at the time of reading. In the latter case, data can be corrected by the ECC circuit as it is read, thus there are no single-bit errors in the reading of data. The data containing errors, however, remains stored in the storage device. Thus, every time a read command for an address in which there is a single-bit error is executed by the buffer storage unit of the storage device, a machine check interrupt for a single-bit error is generated.
If such machine check interrupts are produced more than a predetermined number of times during a certain time interval, the software control shuts off the control mask for the system recovery (SR) interrupt and enters a quiet mode in which the SR class machine check interrupt is not accepted. SR class machine check interrupts, however, include not only correction of single-bit errors, but also the success of command retries, etc. Therefore, it is desirable that the data processing device not enter the quiet mode very often. Accordingly, the second method is disadvantageous when data with a single-bit error in the buffer storage unit is accessed repeated over a short time period.